1. Field of the Invention
The present invention relates generally to output circuits of semiconductor memory devices and, more particularly, to an output circuit for providing data read from a storage element such as a dynamic random access memory (hereinafter referred to as DRAM) to an output terminal.
2. Description of the Background Art
FIG. 4 is a schematic block diagram showing an overall structure of a conventional DRAM. Referring to FIG. 4, address signals applied as an input to address input terminals A.sub.0 -A.sub.9 are stored in an address buffer 1 and then applied to a column decoder 2 and a row decoder 3. Column decoder 2 specifies a column address of a memory cell 5, while row decoder 3 specifies a row address of memory cell 5. Memory cell 5 responds to a read/write specifying input to read data from an addressed memory cell or write data into the memory cell. More specifically, when data reading is specified, data is read from a corresponding address through a sense refresh amplifier and I/O controller 4 and is then output through a data output buffer 8. When data writing is specified, data provided as an input to a data input buffer 7 is written through sense refresh amplifier and I/O controller 4 into a specified address in memory cell 5. A clock generating circuit 6 responds to a column address strobe signal CAS and a row address strobe RAS to generate a clock signal required therein.
FIGS. 5 and 6 are electric circuit diagrams each showing one example of the data output buffer shown in FIG. 4. FIG. 7 is an input/output waveform diagram of the data output buffers shown in FIGS. 5 and 6.
In a data output buffer 8a shown in FIG. 5, n channel transistors 82 and 83 are connected in series between a power source +V and ground, and a signal .phi..sub.1 determined on the basis of the data read from memory cell 5 shown in FIG. 4 is applied to an input of an inverter 81 and also a gate of n channel transistor 83. The signal inverted in inverter 81 is applied to a gate of n channel transistor 82. Data is output through an output terminal 84 from a connection point between a source of n channel transistor 82 and a drain of n channel transistor 83.
In a data output buffer 8b shown in FIG. 6, a p channel transistor 85 is provided in place of inverter 81 and n channel transistor 82 shown in FIG. 5.
In data output buffers 8a and 8b shown in FIGS. 5 and 6, a signal .phi..sub.1 is determined on the basis of the data read from memory cell 5, and when this signal .phi..sub.1 is input to data output buffers 8a and 8b, a signal Dout is output through output terminal 84. At this time, as shown in FIG. 7, the waveform of output signal Dout often becomes abnormal due to mismatching of impedance with an external circuit. Such a phenomenon is normally called a ringing.
As described above, in the conventional DRAM, the waveform abnormality (ringing) often occurs in output signal Dout, whereby troubles often occur in a system including such a DRAM. Especially, in recent years, there is a tendency that the number of output signals increases as 1 .fwdarw. 4 .fwdarw. 8 .fwdarw. 16 . . . with an increase in storage capacity and that allowable margins decrease with an increase in operation speed of the system. Thus, the ringing has become a great problem.